Semiconductor Device with Field Dielectric in an Edge Area

ABSTRACT

A semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.

BACKGROUND

Applications like half bridge circuits use a body diode between a bodyand a drift zone in a semiconductor body of a semiconductor switchingdevice as a freewheeling diode in the reverse mode of the switchingdevice. In the forward-biased mode of the body diode holes and electronsinjected into the drift zone form a high density charge carrier plasmathat results in a low forward voltage drop of the body diode. Asignificant portion of the charge carrier floods an edge area separatingan active area including transistor cells from a side surface of thesemiconductor body. When the switching device changes fromreverse-biased to forward-biased, the body diode changes fromforward-biased to reverse-biased and mobile charge carriers are removedfrom the drift zone.

It is desirable to provide more reliable semiconductor devices.

SUMMARY

According to an embodiment a semiconductor device includes asemiconductor body with transistor cells arranged in an active area andabsent in an edge area between the active area and a side surface of thesemiconductor body. A field dielectric adjoins a first surface of thesemiconductor body and separates, in the edge area, a conductivestructure connected to gate electrodes of the transistor cells from thesemiconductor body. The field dielectric includes a transition from afirst vertical extension to a second, greater vertical extension. Thetransition is in the vertical projection of a non-depletable extensionzone in the semiconductor body, wherein the non-depletable extensionzone has a conductivity type of body/anode zones of the transistor cellsand is electrically connected to at least one of the body/anode zones.

According to another embodiment a semiconductor device includes asemiconductor body with transistor cells arranged in an active area andabsent in an edge area between the active area and a side surface of thesemiconductor body. An interlayer dielectric structure adjoins a firstsurface of the semiconductor body. In the edge area the interlayerdielectric structure separates a gate construction from thesemiconductor body. In the vertical projection of at least a portion ofthe gate construction in the semiconductor body is a non-depletableextension zone of a conductivity type of body/anode zones of thetransistor cells. The non-depletable extension zone is electricallyconnected to at least one of the body/anode zones.

According to a further embodiment a half-bridge circuit includes asemiconductor body with transistor cells arranged in an active area andabsent in an edge area between the active area and a side surface of thesemiconductor body. A field dielectric adjoins a first surface of thesemiconductor body and separates, in the edge area, a conductivestructure from the semiconductor body. The field dielectric includes atransition from a first vertical extension to a second, greater verticalextension. The transition is in the vertical projection of anon-depletable extension zone in the semiconductor body, wherein thenon-depletable extension zone has a conductivity type of body/anodezones of the transistor cells and is electrically connected to at leastone of the body/anode zones.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description and onviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification. The drawings illustrate the embodiments ofthe present invention and together with the description serve to explainprinciples of the invention. Other embodiments of the invention andintended advantages will be readily appreciated as they become betterunderstood by reference to the following detailed description.

FIG. 1A is a schematic cross-sectional view of a portion of asemiconductor device according to an embodiment related to planar gateelectrodes and a stepless transition of a field dielectric between asemiconductor body and a conductive structure.

FIG. 1B is a schematic cross-sectional view of a portion of asemiconductor device according to an embodiment related to planar gateelectrodes and a stepped transition of a field dielectric between asemiconductor body and a conductive structure.

FIG. 1C is a schematic cross-sectional view of a portion of asuperjunction IGFET according to an embodiment related to planar gateelectrodes and a stepless transition of a field dielectric between asemiconductor body and a conductive structure.

FIG. 1D is a schematic cross-sectional view of a portion of asuperjunction IGFET according to an embodiment related to a burieddepletable extension zone and a stepless transition of a fielddielectric between a conductive structure and a semiconductor body.

FIG. 1E is a schematic cross-sectional view of a portion of asuperjunction IGFET in accordance with an embodiment related to buriedgate electrodes.

FIG. 1F is a schematic cross-sectional view of a portion of an MCD(MOS-controlled diode) according to another embodiment.

FIG. 2A is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment with a non-depletable extensionzone surrounding an active area along a circumferential line at aconstant dopant concentration.

FIG. 2B is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment providing a non-depletableextension zone that surrounds an active area and that includes sectionsof enhanced dopant concentration.

FIG. 2C is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment with an enlarged portion of anon-depletable extension zone formed in the vertical projection of agate construction.

FIG. 2D is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment with a non-depletable extensionzone exclusively formed in the vertical projection of a gateconstruction.

FIG. 2E is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment with a non-depletable extensionzone including a section of enhanced dopant concentration in thevertical projection of a gate construction.

FIG. 2F is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment providing a segmentednon-depletable extension zone.

FIG. 2G is a schematic lateral cross-sectional view of a semiconductordevice in accordance with an embodiment with a portion of anon-depletable extension zone formed in the vertical projection of aportion of a gate construction.

FIG. 3 is a schematic cross-sectional view of a portion of asemiconductor device in accordance with another embodiment with anon-depletable extension zone in the vertical projection of a portion ofa gate construction.

FIG. 4 is a schematic diagram comparing switching-off losses forillustrating effects of the embodiments.

FIG. 5A is a schematic circuit diagram of a half-bridge circuitaccording to an embodiment with two n-type IGFETs.

FIG. 5B is a schematic circuit diagram of a half-bridge circuitaccording to an embodiment with a p-type and an n-type IGFET.

FIG. 5C is a schematic circuit diagram of a half-bridge circuitaccording to an embodiment with IGBTs.

FIG. 5D is a schematic circuit diagram of a full-bridge circuitaccording to a further embodiment.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and in which are shownby way of illustrations specific embodiments in which the invention maybe practiced. It is to be understood that other embodiments may beutilized and structural or logical changes may be made without departingfrom the scope of the present invention. For example, featuresillustrated or described for one embodiment can be used on or inconjunction with other embodiments to yield yet a further embodiment. Itis intended that the present invention includes such modifications andvariations. The examples are described using specific language, whichshould not be construed as limiting the scope of the appending claims.The drawings are not scaled and are for illustrative purposes only. Forclarity, the same elements have been designated by correspondingreferences in the different drawings if not stated otherwise.

The terms “having”, “containing”, “including”, “comprising” and the likeare open, and the terms indicate the presence of stated structures,elements or features but do not preclude additional elements orfeatures. The articles “a”, “an” and “the” are intended to include theplural as well as the singular, unless the context clearly indicatesotherwise.

The term “electrically connected” describes a permanent low-ohmicconnection between electrically connected elements, for example a directcontact between the concerned elements or a low-ohmic connection via ametal and/or highly doped semiconductor. The term “electrically coupled”includes that one or more intervening element(s) adapted for signaltransmission may be provided between the electrically coupled elements,for example elements that are controllable to temporarily provide alow-ohmic connection in a first state and a high-ohmic electricdecoupling in a second state.

The Figures illustrate relative doping concentrations by indicating “−”or “+” next to the doping type “n” or “p”. For example, “n⁻” means adoping concentration which is lower than the doping concentration of an“n”-doping region while an “n+”-doping region has a higher dopingconcentration than an “n”-doping region. Doping regions of the samerelative doping concentration do not necessarily have the same absolutedoping concentration. For example, two different “n”-doping regions mayhave the same or different absolute doping concentrations.

FIGS. 1A to 1E refer to controllable semiconductor devices 500 includingactive transistor cells and/or controllable desaturation or injectioncells, for example controllable semiconductor diodes such as MCDs,IGFETs (insulated gate field effect transistors) including MOSFETs(metal oxide semiconductor FETs) in the usual meaning including FETswith metal gates as well as FETs with non-metal gates, JFETs (junctionfield effect transistors), IGBTs (insulated gate bipolar transistors),and thyristors, by way of example.

Each of the semiconductor devices 500 is based on a semiconductor body100 from a single-crystalline semiconductor material such as silicon(Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal(SiGe), gallium nitride (GaN), gallium arsenide (GaAs) or any otherA_(III)Bv semiconductor.

The semiconductor body 100 has a first surface 101 which may beapproximately planar or which may be given by a plane spanned bycoplanar surface sections as well as a mainly planar second surface 102parallel to the first surface 101. A minimum distance between the firstand second surfaces 101, 102 is selected to achieve a specified voltageblocking capability of the semiconductor device 500. A side surface 103connects the first and second surfaces 101, 102.

In a plane perpendicular to the cross-sectional plane the semiconductorbody 100 may have a rectangular shape with an edge length in the rangeof several millimeters or may be disc-shaped with a diameter of severalcentimeters. A normal to the first surface 101 defines a verticaldirection and directions orthogonal to the vertical direction arelateral directions.

The semiconductor body 100 includes a drift zone 120 of a firstconductivity type as well as a pedestal layer 130 between the drift zone120 and the second surface 102.

A dopant concentration in the drift zone 120 may gradually or in stepsincrease or decrease with increasing distance to the first surface 101at least in portions of its vertical extension. According to otherembodiments the dopant concentration in the drift zone 120 may beapproximately uniform. A mean dopant concentration in the drift zone 120may be between 5E12 cm⁻³ and 1E16 cm⁻³, for example in a range from 5E13cm⁻³ to 5E15 cm⁻³. The drift zone 120 may include further dopant zones,e.g. a superjunction structure.

The pedestal layer 130 may have the first conductivity type in case thesemiconductor device 500 is a semiconductor diode, an IGFET or a JFET,may have a second conductivity type, which is complementary to the firstconductivity type, in case the semiconductor device 500 is an IGBT or athyristor or may contain zones of both conductivity types extendingbetween the drift zone 120 and the second surface 102 in case thesemiconductor device 500 is an MCD or an RC-IGBT (reverse conductingIGBT). The dopant concentration in the pedestal layer 130 issufficiently high to form an ohmic contact with a metal directlyadjoining the second surface 102. In case the semiconductor body 100 isbased on silicon Si, a mean dopant concentration for a p-type pedestallayer 130 or p-type zones of the pedestal layer 130 may be at least 1E16cm⁻³, for example at least 5E17 cm⁻³.

The semiconductor devices 500 further includes active, functionaltransistor cells TC in an active area 610, whereas an edge area 690between the side surface 103 and the active area 610 is devoid of anyfunctional transistor cells of the type present in the active area 610.Each active transistor cell TC includes body/anode zones 115 of thesecond conductivity type forming first pn junctions pn1 with the driftzone 120 as well as source zones 110 forming second pn junctions withthe body/anode zones 115. The source zones 110 may be wells extendingfrom the first surface 101 into the semiconductor body 100, for exampleinto the body/anode zones 115.

A gate structure 150 includes a conductive gate electrode 155 which mayinclude or consist of a heavily doped polycrystalline silicon layer or ametal-containing layer as well as a gate dielectric 151 separating thegate electrode 155 from the semiconductor body 100. The gate dielectric151 capacitively couples the gate electrode 155 to channel portions ofthe body/anode zones 115.

In the illustrated embodiments and for the following description, thefirst conductivity type is the n-type and the second conductivity typeis the p-type. Similar considerations as outlined below apply toembodiments with the first conductivity being the p-type and the secondconductivity type being the n-type.

When a voltage applied to the gate electrode 150 exceeds a presetthreshold voltage, electrons accumulate in the channel portions of thebody/anode zones 115 directly adjoining the gate dielectric 151 and forminversion channels short-circuiting the first pn junctions pn1.

The gate structure 150 includes an idle portion 150 a including an idlegate electrode 155 a in the edge area 690. The idle gate electrode 155 aand the gate electrode 155 are electrically and structurally connectedto each other and may be portions of the same layered structure. A gateconstruction 330 may be connected to the gate electrode 155 via the idlegate electrode 155 a.

The gate construction 330 may include at least one of a gate pad, a gatefinger, and a gate runner electrically connected to the gate electrode155, respectively. A gate pad may be a metal pad suitable as a landingpad for a bond wire or another chip-to-leadframe or chip-to-chipconnection like a soldered clip. The gate pad may be arranged between afirst load electrode 310 and the side surface 103 or in a center portionof the semiconductor body 100. A gate runner may be a metal linesurrounding the active area 610. A gate finger may be a metal lineseparating the active areas 610 in separated cell fields. An interlayerdielectric 210 separates the gate construction 330 from thesemiconductor body 100 and may insulate the gate electrode 155 from thefirst load electrode 310.

A conductive structure 157 structurally and electrically connects theidle gate electrode 155 a with the gate construction 330 or with a gatecontact structure 315 g extending from the gate construction 330 intothe interlayer dielectric 210. The conductive structure 157 can be apart of an integrated gate resistor or polycrystalline silicon diode orcan be omitted below the gate construction 330. A portion of theinterlayer dielectric 210 between the conductive structure 157 and thesemiconductor body 100 forms a field dielectric 211. The fielddielectric 211 has a transition Tr between a first vertical extensionclose to the gate dielectric thickness in a portion directly adjoiningthe idle gate electrode 155 a and a second vertical extension, which isgreater than the first vertical extension, in a section directlyadjoining the gate construction 330 or the gate contact structure 315 g.The transition Tr may be continuous or may include one or more steps.

The gate electrode 155, the idle gate electrode 155 a and the conductivestructure 157 may be homogeneous structures or may have a layeredstructure including one or more metal containing layers. According to anembodiment the gate electrode 155, the idle gate electrode 155 a and theconductive structure 157 may include or consist of a heavily dopedpolycrystalline silicon layer.

The gate dielectric 151 may include or consist of a semiconductor oxide,for example thermally grown or deposited silicon oxide, semiconductornitride, for example deposited or thermally grown silicon nitride or asemiconductor oxynitride, for example silicon oxynitride.

The first load electrode 310 may be, e.g., an anode electrode of an MCD,a source electrode of an IGFET or an emitter electrode of an IGBT.Contact structures 315 electrically connect the first load electrode 310with the body/anode zones 115 and the source zones 110. The first loadelectrode 310 may be or may be electrically coupled or connected to afirst load terminal L1, for example the anode terminal of an MCD, theemitter terminal of an IGBT or the source terminal of an IGFET.

A second load electrode 320, which directly adjoins the second surface102 and the pedestal layer 130, may form or may be electricallyconnected to a second load terminal L2, which may be the cathodeterminal of an MCD, the collector terminal of an IGBT or the drainterminal of an IGFET.

Each of the first and second load electrodes 310, 320 may consist of orcontain, as main constituent(s), aluminum (Al), copper (Cu), or alloysof aluminum or copper, for example AlSi, AlCu or AlSiCu. According toother embodiments, at least one of the first and second load electrodes310, 320 may contain, as main constituent(s), nickel (Ni), titanium(Ti), tungsten (W), tantalum (Ta), vanadium (V), silver (Ag), gold (Au),platinum (Pt), and/or palladium (Pd). For example, at least one of thefirst and second load electrodes 310, 320 may include two or moresub-layers, wherein each sub-layer contains one or more of Ni, Ti, V,Ag, Au, Pt, W, and Pd as main constituent(s), e.g., a silicide, anitride and/or an alloy.

The interlayer dielectric 210 may include one or more dielectric layersfrom silicon oxide, silicon nitride, silicon oxynitride, doped orundoped silicon glass, for example BSG (boron silicate glass), PSG(phosphorus silicate glass) or BPSG (boron phosphorus silicate glass),by way of example.

In the vertical projection of the transition Tr in the field dielectric211, the semiconductor body 100 includes a non-depletable extension zone170 of the second conductivity type. The non-depletable extension zone170 is electrically connected to at least one of the body/anode zones115 and may directly adjoin or overlap with an outermost of thebody/anode zones 115, by way of example. A net dopant concentration inthe non-depletable extension zone 170 is sufficiently high such that thenon-depletable extension zone 170 is not completely depleted when therespective semiconductor device 500 is operated within its maximumblocking ratings.

According to an embodiment the net dopant concentration of thenon-depletable extension zone 170 is such that when a maximum voltage isapplied between the first and second load electrodes 310, 320 thenon-depletable extension zone 170 is not depleted regardless of a gatevoltage applied to the gate construction 330 provided that the appliedgate voltage is within the maximum ratings of the semiconductor device500 for the gate voltage.

When the semiconductor device 500 is operated with the forward-biasedfirst pn junction pn1 between the body/anode zones 115 and the driftzone 120, the body/anode zones 115 inject holes and the pedestal layer130 injects electrons into the drift zone 120. The injected chargecarriers form a charge carrier plasma in both the active area 610 andthe edge area 690. When the semiconductor device 500 commutates afterreverse-biasing the first pn junction pn1 the second load electrode 320drains off electrons and the first electrode 310 drains off holes. Holesflowing from the edge area 690 to the first load electrode 310 travel tothe outermost contact structure 315 that electrically connects the firstload electrode 310 with the outermost source and body/anode zones 110,115 of the active area 610. The hole current flow results in high holeconcentrations and high hole current densities in a portion of the edgearea 690 in the vertical projection of the conductive structure 157.

On the other hand in areas of the semiconductor body 100 below thetransition Tr the electric surface field strength is high resulting inincreased charge carrier multiplication. As a result of the surfacefield strength and the hole current flow, the dynamic breakdown voltageis locally reduced and the field dielectric 211 can be irreversiblydamaged.

The non-depletable extension zone 170 effects that a surface electricfield is only formed beyond a minimum hole current density whichcompensates for the charge of the stationary p-type dopants in thenon-depletable extension zone 170. Increasing the p-type dopantconcentration reduces the surface electric field strength such that thedynamic breakdown voltage may be locally increased. The field dielectric211 is more reliable and in a half-bridge circuit the semiconductordevice 500 can sustain steeper and faster gate signals of thecommutating switch of the half-bridge circuit.

In case of a silicon semiconductor body 100, the effective dose ofp-type dopants in the non-depletable extension zone is greater than2.5E12 cm⁻², for example at least 1E13 cm⁻². According to an embodimentthe p-type dopant dose in the non-depletable extension zone 170 isgreater than 2E13 cm⁻². The non-depletable extension zone 170 directlyadjoins or overlaps or is electrically connected with the p-typebody/anode zone 115 of the outermost transistor cell TC of the activearea 610 with reference to the edge area 690.

Within the non-depletable extension zone 170 the impurity concentrationis constant or decreases by not more than 50% between a starting pointof the transition Tr, where a vertical extension of the transition Trstarts to increase from the first vertical extension, and a referencepoint at a distance of at least 1 μm to the starting point. According toan embodiment, the impurity concentration is constant or deviates by notmore than 50% over a distance of at least 3 μm, for example at least 8μm, to the starting point in the direction along which the transition Trincreases.

A vertical extension of the non-depletable extension zone 170perpendicular to the first surface 101 may exceed a vertical extensionof the body/anode zones 115 of the transistor cells TC.

The semiconductor device 500 of FIG. 1B differs from the semiconductordevice 500 of FIG. 1A in that a dedicated contact structure 315 aelectrically connects the first load electrode 310 directly with thenon-depletable extension zone 170 in the edge area 690. The dedicatedcontact structure 315 a is spatially separated from any source zone 110.The transition Tr of the field dielectric 211 includes a step thatcorresponds to a vertical step in the conductive structure 157.

The semiconductor device 500 of FIG. 1C is a superjunction IGFET basedon the semiconductor device 500 of FIG. 1A. The first load electrode 310is effective as source electrode electrically connected to a sourceterminal S. The second load terminal 320 is effective as drain electrodeD. An edge termination construction 195 formed in a portion of the edgearea 690 directly adjoining the side surface 103 may include a drainelectrode construction 325 on a front side of the semiconductor body 100opposite to the second load electrode 320.

The drift zone 120 may include a superjunction structure 180 includingfirst zones 181 of the first conductivity type and second zones 182 ofthe second conductivity type. At least the second zones 182 or at leastthe first zones 181 may be columnar structures formed by implantatione.g. in successive epitaxy and implantation steps. According to otherembodiments the second zones 182 are formed by depositing materialcontaining p-type dopants into trenches temporally formed between thefirst zones 181 or by introducing dopants through sidewalls of trenchestemporally extending from the first surface 101 into the drift zone 120.

The lateral cross-sectional areas of the second zones 182 may becircles, ovals, ellipses or rectangles with or without rounded cornersand the first zones 181 may form a grid with the second zones 182arranged in the meshes. According to another embodiment lateralcross-sectional areas of the first zones 181 are circles, ellipses,ovals or rectangles with or without rounded corners and the second zones182 form a grid with the first zones 181 arranged in the meshes. Inaccordance with a further embodiment the first and second zones 181, 182form a regular stripe pattern, wherein the stripes may extend through asignificant portion of the active area 610 or may cross the active area610.

The dopant concentrations in the first and second zones 181, 182 may beadjusted to each other such that the portion of the drift zone 120including the superjunction structure 180 can be completely depleted ina reverse blocking mode of the semiconductor device 500.

According to an embodiment, the first and second zones 181, 182 may beformed exclusively within the active area 610, whereas the edge area 690or a gate area in the vertical projection of gate constructions such asgate pads, gate fingers and/or gate runners are devoid of anysuperjunction structure, for example devoid of any first and secondzones 181, 182. For example, the semiconductor device 500 may include asuperjunction structure with first and second zones 181, 182 in theactive area 610 and only intrinsic or weakly doped regions of the firstconductivity type having a lower net impurity concentration than thefirst zones 181 in the edge area 610 and in the vertical projection ofgate areas. Alternatively first zones 181 and second zones 182 mayoverlap in the edge area 610 and/or in the vertical projection of gateareas to form regions of a low net dopant concentration in the concernedareas.

According to the illustrated embodiment, a superjunction structure withfirst and second zones 181, 182 is formed in both the active area 610and the edge area 690. A depletable extension zone 175 may directlyadjoin to or overlap with the non-depletable extension zone 170 and one,some or all of the second zones 182 in the edge area 690 along theillustrated cross-sectional line.

The p-type dopant dose in the depletable extension zone 175 issufficiently low such that the depletable extension zone 175 iscompletely depleted in the blocking mode of the semiconductor device500. For example, the implanted p-type dopant dose in the depletableextension zone 175 may result from an implant dose of at most 3.5E12cm⁻² resulting, when considering segregation effects, in a remnanteffective p-type dopant dose of at most 2E12 cm⁻² in silicon.

A vertical extension of the non-depletable extension zone 170perpendicular to the first surface 101 may exceed a vertical extensionof the body/anode zones 115 of the transistor cells TC. For example, inthe reverse biased mode an edge of a depletion zone in the semiconductorbody 100 oriented to the first surface 101 may have a greater distanceto the first surface 101 in the non-depletable extension zone 170 thanin p-type structures including the body/anode zones 115 and the secondzones 182.

When the semiconductor device 500 commutates the first and second zones181, 182 are depleted, wherein in the second zones 182 holes travelalong the vertical direction and reach the first surface 101. In theedge area 690, a resulting hole current at the first surface 101 intothe direction of the next contact structure 315 adds to a hole currentresulting from the holes injected into the drift zone 120 in theforward-biased mode of the body pn junction pn1. As a result, insuperjunction devices the effect discussed above is more significantsince a greater portion of the holes is first guided to the firstsurface 101 and then guided along the first surface into the directionof the first contact 315. The effect may be even more pronounced sincein the active area 610 the second zones 182 accelerate the holedischarge and, when finally the hole current in the active area 610pinches off, the edge area 690 still discharges holes and due to leakageinductance carries further increased hole current densities.

The depletable extension zone 175 reduces the resistance effective forthe total hole current flow from at least one or some of the secondzones 182 of the edge area 690 to a contact structure 315 electricallyconnecting the first load electrode 310 with the extension zones 170,175 and may reduce the switching losses.

In addition, the comparatively high hole current density significantlyreduces the dynamic breakdown voltage of the field dielectric 211.Instead, the non-depletable extension zone 170 locally decreases thesurface electric field strength without significantly adverselyaffecting the lateral voltage blocking capability despite that the holecurrent densities are increased by approximately one order of magnitude.

The semiconductor device 500 of FIG. 1D differs from the superjunctionIGFET of FIG. 1C in that the depletable extension zone 175 is connectedto all second zones 182 in the edge area 690 between the non-depletableextension zone 170 and the side surface 103 and in that a spacer zone173 of the first conductivity type separates the depletable extensionzone 175 from the first surface 101. The spacer zone 173 reduces theeffect of holes flowing into direction of the active area 610 duringcommutation on the field dielectric 211. The surface electric field ismore homogenous, the integrated ionization charge along the hole currentflow is reduced and the dynamic breakdown voltage is further increased.

The semiconductor device 500 of FIG. 1E is an IGFET based on thesemiconductor device 500 of FIG. 1A. A field stop layer 128 having adopant concentration at least twice as high as in the drift zone 120separates the drift zone 120 from the pedestal layer 130. In anotherembodiment a buffer layer with a dopant concentration that is lower thanin the first zones 181 is formed between the pedestal layer 130 and thesecond zones 182.

The transistor cells TC are vertical transistor cells TC with the gatestructures 150 including buried gate electrodes 155 extending from thefirst surface 101 into the semiconductor body 100. A dielectricstructure 205 may separate the first load electrode 310 from the buriedgate electrodes 155.

Other embodiments may refer to IGBTs on the basis of the IGFETs of FIGS.1C to 1E with the pedestal layer 130 having the p-type or includingp-type zones. For IGBTs, the first load electrode 310 is effective as anemitter electrode forming or electrically connected or coupled to anemitter terminal. The second load electrode 320 is effective ascollector electrode and forms or is electrically connected to acollector terminal.

The semiconductor device 500 of FIG. 1F is an MCD that may include abarrier layer 121 between the body/anode zones 115 and the drift zone120. The pedestal layer 130 may include first zones 131 of the firstconductivity type and second zones 132 of the second conductivity typeextending between the drift zone 120 and the second surface 102,respectively. The transistor cells TC are switched off in the normalforward-biased state of the MCD. Before commutation, a potential appliedto the gate electrode 155 generates inversion layers from the sourcezones 110 to the drift zone 120 through the body/anode zones 115. Theinversion layers short-circuit the first pn junction pn1 between thebody/anode zones 115 and the drift zone 120 and reduce or suppress holeinjection from the body/anode zones 115 into the drift zone 120. Thecarrier plasma in the drift zone 120 is reduced and the recovery chargecan be decreased. The barrier layer 121 reduces the lateral voltage dropalong the first pn junction pn1 to avoid injection between the gatestructures 150 in a distance to the inversion layers.

According to an embodiment referring to IGFETs including MGD (MOS gateddiode) cells the semiconductor device 500 may include IGFET cells andMGD cells with gate electrodes electrically connected to the first loadelectrode 310. In the reverse conducting mode of the semiconductordevice 500 the current flow between the first and second load electrodes310, 320 results in that the body/anode zones 115 are negatively biasedwith respect to the first load electrode 310 and the gate electrodes ofthe MGDs and an inversion layer may be formed in the body/anode zones115. If in the reverse mode the total current through the semiconductordevice 500 is above an average current flow density threshold, it istypically dominated by a unipolar current flow reducing the electriclosses compared to the case of a total current flow across the first pnjunctions pn1.

FIGS. 2A to 2G refer to lateral cross-sections of semiconductor devices500 for illustrating embodiments of the lateral extension of thenon-depletable extension zones 170 of any of the semiconductor devices500 of FIGS. 1A to 1E.

An edge area 690 devoid of functional transistor cells separates anactive area 610, which includes the functional transistor cells, fromthe side surface 103 of a semiconductor body 100. The edge area 690includes gate area 695 in the vertical projection of a gate construction330. In the illustrated embodiment the gate area 695 is assigned to agate construction 330 including a single gate pad. According to otherembodiments, the gate construction 330 may include more than one gatepad, a gate runner, and/or one or more gate fingers and the gate area695 may include further portions in the vertical projection of gatefingers and/or gate runners that form sections of electric connectionsbetween gate electrodes and a gate pad in a metallization plane. Gatepad and gate area 695 may be arranged in a corner or along one of thelateral sides of the semiconductor body 100. A gate runner may surroundthe active area 610. A gate finger may separate the active areas 610 inseparate cell fields.

FIG. 2A shows a non-depletable extension zone 170 completely surroundingthe active area 610 along a circumferential line CL sparing the gatearea 695. Along the circumferential line CL, a net dopant concentrationof the non-depletable extension zone 170 is constant. A depletableextension zone 175 may directly adjoin or overlap with thenon-depletable extension zone 170 in the edge area 690 at a sideoriented to the side surface 103.

FIG. 2B refers to an embodiment with a first, along the circumferentialline CL approximately constant net dopant concentration p1 ⁺ in firstsections 170 a of the non-depletable extension zone and an enhancedsecond net dopant concentration p2 ⁺, which is higher, e.g. at leasttwice as high as the first net dopant concentration p1 ⁺, in secondsections 170 b. The second sections 170 b may be laterally curvedsections close to the corners of the semiconductor body 100 and/orsections between the active area 610 and the gate area 695. The firstsections 170 a may be straight sections connecting the second sections170 b.

The second sections 170 b may be formed by implanting the concerneddopants at a locally increased implant dose or by performing a firstimplant with uniform implant dose along the circumferential line CL anda second implant which is selectively effective in the second sections.

The higher dopant concentration in the second sections 170 b maycompensate for an increased hole current close to the corners and to thegate area 695 and resulting from increased hole current density in widerportions of the semiconductor body 100 without source and body contacts,e.g. in the gate area 695 and close to the corners, where more holes areallocated per length unit of the extension zones 170, 175 along thecircumferential line CL.

The dopant concentration profiles of the non-depletable extension zones170 along the circumferential line CL may include further sections witha dopant concentration between the first and the second dopantconcentrations. The first sections 170 a of the non-depletable extensionzone may contain a dopant dose of at least 2.5E12 cm⁻², for example atleast 1E13 cm⁻² or greater than 2E13 cm⁻². The second sections 170 b maycontain a dopant dose which is at least twice as high as the firstdopant dose, for example at least four times as high as the first dopantdose.

In the semiconductor device 500 in FIG. 2C the non-depletable extensionzone 170 includes an enlarged portion 170 x formed in the verticalprojection of a gate pad in the gate area 695. The enlarged portion 170x may extend over the complete gate area 695 and may overlap thecomplete vertical projection of a gate construction including at least agate pad. A further portion of the non-depletable extension zone 170surrounds the active area 610 as described with reference to FIG. 2A.

In FIG. 2D the non-depletable extension zone 170 is exclusively formedin the vertical projection of a gate pad in the gate area 695. Thenon-depletable extension zone 170 may include further sections infurther sections of the gate area 695 assigned to gate fingers and/orgate runners.

The semiconductor device 500 of FIG. 2E differs from the one in FIG. 2Bin that the non-depletable extension zone 170 includes a section ofenhanced dopant concentration 170 b that extends over the complete or atleast a main portion of the gate area 695 and overlaps with at least amain portion of the vertical projection of a gate pad. Thenon-depletable extension zone 170 may include further sections infurther sections of the gate area 695 assigned to gate fingers and/orgate runners.

FIG. 2F refers to an embodiment with the non-depletable extension zone170 including isolated segments arranged along the circumferential lineCL. The segments may be curved sections in the corners of thesemiconductor body 100 and/or sections between the active area 610 andthe gate area 695.

FIG. 2G refers to a layout with the gate area 695 arranged along one ofthe lateral sides and symmetric with respect to a lateral center axis ofthe semiconductor body 100. Sections of the depletable andnot-depletable extension zones 175, 170 may completely span the gatearea 695. In a further embodiment, the gate pad may be located in themiddle of the active area 610.

FIG. 3 refers to semiconductor devices 500 with a non-depletableextension zone 170 formed at least in a portion of the verticalprojection of a gate construction 330. The non-depletable extension zone170 may extend over at least 40% of the vertical projection of the gateconstruction 330, for example over at least 80%. According to anembodiment the non-depletable extension zone 170 extends over the wholevertical projection of the gate construction 330. The configuration ofthe gate construction 330, the conductive structure 157 electricallyconnecting the gate construction 330 with idle gate electrodes 155 a aswell as the non-depletable extension zone 170 as shown in FIG. 3 can becombined with any of the semiconductor devices 500 described withreference to FIGS. 1A to 1F. An interlayer dielectric structure 200adjoins a first surface 101 of the semiconductor body 100. In the edgearea 690 the interlayer dielectric structure 200 separates a gateconstruction 330 from the semiconductor body 100. The interlayerdielectric structure 200 may include a conductive structure 157, whereina field dielectric 211 separates the conductive structure 157 from thesemiconductor body 100 and a capping dielectric 212 separates theconductive structure 157 from the gate construction 330.

In the vertical projection of at least a portion of the gateconstruction 330 in the semiconductor body 100 is a non-depletableextension zone 170 of a conductivity type of body/anode zones 115 of thetransistor cells TC. The gate construction 330 may be a gate padsuitable as a landing pad for a bond wire or another chip-to-leadframeor chip-to-chip connection like a soldered clip. The gate pad can be indirect connection with the conductive structure 157. The conductivestructure 157 can be a part of an integrated gate resistor orpolycrystalline silicon diode or can be omitted below the gate pad. Forfurther details reference is made to the description of FIGS. 1A to 2G.

During commutation, the non-depletable extension zones 170 reduce aresistance effective for a hole current flow between the edge area 690and the outermost contact of the first load electrode 310 oriented tothe edge area 690. Compared to depletable extension zones, which arefully depleted in case of the hole current flow and, consequently, havea comparatively high ohmic resistance, the non-depletable extension zone170 is not fully depleted and, consequently, improves the depletionprocess of holes and reduces dynamic switching losses. While withoutnon-depletable extension zones 170 a capacity of the gate construction330 adds to the gate-to-drain capacity C_(gd) after depletion of thesecond zones 182, the non-depletable extension zone 170 shields the gateconstruction 330 such that the gate-to-drain capacity C_(gd) is notincreased or is increased to a lower degree resulting in reducedswitching losses.

The diagram of FIG. 4 schematically shows the switching losses Eoff as afunction of the load current Isat. Comparative examples 791 withoutnon-depletable extension zones show higher switching losses ascomparable devices 792 including non-depletable extension zones. Thenon-depletable extension zones reduce the commutation losses. Since inresonant applications energy capacitively stored in the semiconductordevice 500 is recovered, losses resulting from a gate construction 330may contribute to a third of the overall commutation losses.

FIGS. 5A to 5D refer to electronic circuits 700 including one or morehalf-bridge circuits 710 based on two semiconductor switching devices711, 712 with load current paths connected in series between Vdd andGnd. The semiconductor switching devices 711, 712 may be IGFETs orIGBTs. At least one of the semiconductor switching devices 711, 712 maybe or may include one of the semiconductor devices 500 of the previousfigures. The half-bridge circuit 710 or the complete electronic circuit700 may be integrated in a power module.

The electronic circuit 700 may include a gate driver circuit 720generating and driving a first gate signal at a first driver terminalGout1 and a second gate signal at a second driver terminal Gout2. Thefirst and second driver terminals Gout1, Gout2 are electrically coupledor connected to gate terminals G of the semiconductor switching devices711, 712. The gate driver circuit 720 controls the gate signals suchthat during regular switching cycles the first and second switchingdevices 711, 712 are alternatingly in the on state. During desaturationcycles, the gate driver circuit 720 may apply desaturation pulses beforeswitching one of the switching devices 711, 712 into the on state.

In FIG. 5A the switching devices 711, 712 are n-IGFETs with a sourceterminal S of the first switching device 711 and a drain terminal D ofthe second switching device 712 electrically connected to a switchingterminal Sw.

In FIG. 5B the first switching device 711, 712 is a p-IGFET and thesecond switching device 712 is an n-IGFET.

In FIG. 5C the switching devices 711, 712 are n-channel IGBTs with anemitter terminal E of the first switching device 711 and a collectorterminal C of the second switching device 712 electrically connected toa switching terminal Sw.

FIG. 5D shows an electronic circuit 700 with two half-bridges 710 whoseload paths are connected in parallel and operated in a full-bridgeconfiguration. A load 900, e.g. an inductive load, may be connected tothe switching terminals Sw of the two half-bridges 710. The load 900 maybe a motor winding, an inductive cooking plate or a transformer windingin a switched-mode power supply, by way of example. According to anotherembodiment the electronic circuit 700 may include three half-bridges 710for driving a motor with three windings wherein each winding isconnected between a star node of the motor windings and one of theswitching terminals Sw of the half bridges 710.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor body comprising transistor cells arranged in an activearea and absent in an edge area between the active area and a sidesurface of the semiconductor body; a field dielectric adjoining a firstsurface of the semiconductor body and separating, in the edge area, aconductive structure connected to gate electrodes of the transistorcells from the semiconductor body, the field dielectric comprising atransition from a first to a second, greater vertical extension; and anon-depletable extension zone of a conductivity type of body/anode zonesof the transistor cells and electrically connected to at least one ofthe body/anode zones, wherein the transition is in the verticalprojection of the non-depletable extension zone, wherein thenon-depletable extension zone surrounds the active area at uniformwidth.
 2. The semiconductor device of claim 1, wherein thenon-depletable extension zone is electrically connected to a metallicload electrode.
 3. The semiconductor device of claim 1, wherein thenon-depletable extension zone has an effective dopant dose greater than2.5E12 cm⁻².
 4. The semiconductor device of claim 1, further comprising:a depletable extension zone of the conductivity type of the body/anodezones, directly adjoining the non-depletable extension zone, andarranged between the non-depletable extension zone and the side surface.5. The semiconductor device of claim 4, wherein the depletable extensionzone has an effective dopant dose of at most 2.0E12 cm⁻².
 6. Thesemiconductor device of claim 4, further comprising: a spacer zonebetween the first surface and the depletable extension zone and forminga pn junction with the depletable extension zone.
 7. The semiconductordevice of claim 1, wherein the conductive structure is a section of anelectric connection between a gate construction and gate electrodes ofthe transistor cells.
 8. The semiconductor device of claim 1, whereinthe non-depletable extension zone directly adjoins a body/anode zone ofat least one of the transistor cells.
 9. The semiconductor device ofclaim 1, wherein a vertical extension of the non-depletable extensionzone perpendicular to the first surface exceeds a vertical extension ofthe body/anode zones of the transistor cells.
 10. The semiconductordevice of claim 1, further comprising: first zones of a firstconductivity type opposite to a second conductivity type given by theconductivity type of the body/anode zones; and second zones of thesecond conductivity type, the first and the second zones alternatelyarranged in the semiconductor body in the active area, wherein in theactive area, the second zones directly adjoin the body/anode zones andthe first zones form pn junctions with the body/anode zones.
 11. Thesemiconductor device of claim 1, wherein an impurity concentration inthe non-depletable extension zone does not decrease by more than 50%between a starting point of the transition, where a vertical extensionof the transition starts to increase from the first vertical extension,and a reference point at a distance of at least 3 μm to the startingpoint.
 12. The semiconductor device of claim 1, further comprising: ametal gate pad in a vertical projection of a gate area of the edge area,wherein the gate area is in a corner or along one lateral side of thesemiconductor body, wherein a portion of the non-depletable extensionzone is formed along a line separating the active area and the gatearea.
 13. The semiconductor device of claim 1, wherein along acircumferential line around the active area a net dopant concentrationof the non-depletable extension zone is constant.
 14. The semiconductordevice of claim 1, further comprising: first zones of a firstconductivity type opposite to a second conductivity type given by theconductivity type of the body/anode zones; and second zones of thesecond conductivity type, the first and the second zones alternatelyarranged in the semiconductor body in the active area and the edge area,wherein in the active area, the second zones directly adjoin to thebody/anode zones and the first zones form pn junctions with thebody/anode zones.
 15. The semiconductor device of claim 14, wherein thenon-depletable extension zone overlaps with the second zones, andwherein along a circumferential line around the active area, a netdopant dose of the non-depletable extension zone is constant.
 16. Thesemiconductor device of claim 14, further comprising: a depletableextension zone of the conductivity type of the body/anode zones, whereinthe depletable extension zone directly adjoins the non-depletableextension zone and at least one of the second zones in the edge area.17. The semiconductor device of claim 16, further comprising: a spacerzone between the first surface and the depletable extension zone andforming a pn junction with the depletable extension zone.
 18. Thesemiconductor device of claim 1, wherein the non-depletable extensionzone has an effective dopant dose greater than 2E13 cm⁻².
 19. Thesemiconductor device of claim 1, wherein the non-depletable extensioncomprises straight first sections with a constant first net dopantconcentration and laterally curved second sections, wherein the firstsections connect the second sections and a second net dopantconcentration of the second sections is at least twice as high as thefirst net dopant concentration.
 20. A half-bridge circuit, comprising: asemiconductor body comprising transistor cells arranged in an activearea and absent in an edge area between the active area and a sidesurface of the semiconductor body; a field dielectric adjoining a firstsurface of the semiconductor body and separating, in the edge area, aconductive structure connected to gate electrodes of the transistorcells from the semiconductor body, the field dielectric comprising atransition from a first to a second, greater vertical extension; and anon-depletable extension zone of a conductivity type of body/anode zonesof the transistor cells and electrically connected to at least one ofthe body/anode zones, wherein the transition is in the verticalprojection of the non-depletable extension zone, wherein thenon-depletable extension zone surrounds the active area at uniformwidth.